SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Kemet – C0805C104M5UAC
7.1.3 PLL Layout Requirements
The SiI 0680A uses a high speed Phase Lock Loop (PLL) for clock generation. The layout of this high-speed analog circuit is
critical to the proper operation of the circuit. Power and Ground Planes should be used with the Ground Plane located directly
under the top external layer.
Isolated “islands” for power and ground plane should be used to isolate high-speed digital currents from the PLL circuitry. The
isolated planes should be identical in size and shape. Figures 7-2 and 7-3 show an example 4-layer layout.
The SiI 0680A’s pin PLL_VDD (pin 2) should be connected to the isolated PLL_VDD plane. This plane should be completely
isolated with no connection to the main power plane.
The SiI 0680A’s pin PLL_GND (pin 6) should be connected to the isolated PLL_GND plane. The “island” should be connected
to the ground plane with a narrow “bridge” of at least 0.015” width of copper. Locate this “bridge” directly under L1 as shown
in Figure 7-2.
The PLL components (C2, C3, C4, C5, R1, R2, and R3) should be mounted on top of the PLL_GND “island”. The island
should cover all areas under the components, their pads and connected traces. No PLL circuitry should be exposed (be
located on top of) to either the main ground plane or cut in the planes. Only the listed PLL components should connect to the
“island”. No other ground connections should be made there.
It is important to keep the trace lengths short. No high-speed digital signals should be allowed to pass through, above or
below, any portion of the power and ground “islands”. Take extra care to make sure the data bits located on pins 8 through 15
are routed clear of the “islands”.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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