SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
6. Clocking System
The SiI 0680A ASIC utilizes an on-chip 400 MHz PLL to synthesize the clock frequencies required to support the various ATA
modes. The clock frequency for the ATA UDMA mode logic is software programmable for 66, 100 or 133 MHz. The ATA
clock can also be disabled. The clock frequency for the PCI interface logic and most of the device is derived from the 33 MHz
PCI bus clock.
The clock tree for ATA Channel #1 is offset by 5 nsec relative to the clock tree for IDE Channel #0. This reduces the amount
of simultaneous switching activity within the core and on external pins.
Several test modes within the clocking system are required for PLL and internal scan testing. These topics are covered in
Chapter 10.
SYS_NAND_TEST
JP
Test
Register
1
0
Nand Tree
PCI_INTA_N
MEM_CS_N
Normal Function
Normal Function
0
1
4K
RST_PLL_TEST
PCI_IDSEL
BA5_EN
&
&
SCAN_MODE
&
1
0
PLL_TEST_CLK_SEL
P_CLK
33 MHz
2
2
3
&
SYS_IDE_CLKSEL[1:0]
PLL_TEST_MODE
3
2
TEST_MODE
PCI_GNT_N
&
0
1
133 MHz
1
I0_CLK
I1_CLK
0
( FB Clock )
(Ref Clock)
100 MHz
PLL
PCI_CLK
0
1
0
1
5ns
(Test Clock)
2
2
2
IDE0_DMARQ
PCI_CLK x 2
(Test Clock)
(Test Clock)
IDE0_CBLID_N
IDE1_CBLID_N
SCAN_EN
To all scan flip flops
Figure 6-1: SiI 0680A Clocking System and Test Feature Diagram
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
37
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