Si3220/Si3225
Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
Supply Voltage, Si3200 and Si3220/Si3225
High Battery Supply Voltage, Si3200
2
Low Battery Supply Voltage, Si3200
TIP or RING Voltage, Si3205
Symbol
V
DD
, V
DD1
–V
DD4
V
BATH
V
BAT
,V
BATL
V
TIP
,V
RING
Test
Condition
Continuous
10 ms
Continuous
Continuous
Pulse < 10
µs
Pulse < 4
µs
Value
–0.5 to 6.0
0.4 to –104
0.4 to –109
V
BATH
Unit
V
V
V
TIP, RING Current, Si3200
STIPAC, STIPDC, SRINGAC, SRINGDC Current,
Si3220/Si3225
Input Current, Digital Input Pins
Si3220/25 Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad, or GND1 to GND2)
5
Si3220/25 Digital Ground Differential Voltage (GND3
to GND4)
5
Si3220/25 Analog to Digital Ground Differential Volt-
age (GND1/GND2/ePad to GND3/GND4)
5
Digital Input Voltage
Operating Temperature Range
Storage Temperature Range
Si3220/Si3225 Thermal Resistance, Typical
3
(TQFP-64 ePad)
Si3200 Thermal Resistance, Typical
3
(SOIC-16
ePad)
Continuous Power Dissipation, Si3200
4
Continuous Power Dissipation, Si3220/25
I
TIP
, I
RING
–104
V
BATH
–15
V
BATH
–35
±100
±20
±10
±50
±50
±200
mA
mA
mA
mV
mV
mV
I
IN
∆V
GNDA
∆V
GNDD
∆V
GND,A–D
V
IND
T
A
T
STG
θ
JA
θ
JA
P
D
P
D
Continuous
–0.3 to (
V
DDD
+ 0.3)
V
–40 to 100
°C
–40 to 150
°C
25
°C/W
55
T
A
= 85 °C,
SOIC-16
T
A
= 85 °C,
TQFP-64
1
1.6
°C/W
W
W
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2.
The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs.
3.
The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC
®
User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
4.
On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal
reliability, junction temperatures above 140 °C should be avoided.
5.
The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the
GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not
exceeded under any operating condition in addition to providing thermal dissipation.
4
Rev. 1.0
SILICONIMAGE [ Silicon image ]
