SiM3C1xx
Table 3.2. Power Consumption
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Digital Core Supply Current
2,3,4,5
Normal Mode
—Full speed
I
I
I
I
I
I
F
F
= 80 MHz,
= 40 MHz
—
33
36.5
mA
DD
DD
DD
DD
DD
DD
AHB
with code executing from Flash,
peripheral clocks ON
APB
F
= F
= 20 MHz
—
—
—
10.5
2.0
22
13.3
3.8
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,5
Normal Mode
—Full speed
F
= 80 MHz,
= 40 MHz
24.9
AHB
with code executing from Flash,
peripheral clocks OFF
F
APB
F
= F
= 20 MHz
—
—
—
7.8
1.2
10
3
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,6
Power Mode 1
—Full speed
F
= 80 MHz,
= 40 MHz
30.5
35.5
AHB
with code executing from RAM,
peripheral clocks ON
F
APB
F
= F
= 20 MHz
—
—
—
8.5
1.7
20
10
3.5
23
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,6
Power Mode 1
—Full speed
F
= 80 MHz,
= 40 MHz
AHB
with code executing from RAM,
peripheral clocks OFF
F
APB
F
= F
= 20 MHz
—
—
—
5.3
1.0
19
7.3
2.8
22
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4
Power Mode 2
—Core halted
F
= 80 MHz,
= 40 MHz
AHB
with peripheral clocks ON
F
APB
F
= F
= 20 MHz
—
—
—
—
7.8
1.3
9.7
3
mA
mA
µA
AHB
APB
APB
F
V
V
= F
= 2.5 MHz
AHB
2,3
Power Mode 3
= 1.8 V, T = 25 °C
175
250
—
—
DD
DD
A
= 3.0 V, T = 25 °C
µA
A
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Preliminary Rev. 0.8
7
SILICON [ SILICON ]
