SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB1.9/
TRACECLK
Standard I/O /ETM 46 A28 XBR0
ADC1.9
ADC1.8
ADC1.7
ADC1.6
PB1.10
PB1.11
PB1.12
PB1.13
PB1.14
PB1.15
PB2.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
43 A26 XBR0
42 A25 XBR0
41 D3 XBR0
40 A24 XBR0
39 A23 XBR0
38 A22 XBR0
37 B17 XBR1
A23m/
A15
DMA0T1
DMA0T0
A22m/
A14
A21m/
A13
A20m/
A12
ADC0T15
WAKE.0
ADC1.5
CS0.10
A19m/
A11
ADC1T15
WAKE.1
ADC1.4
CS0.11
A18m/
A10
WAKE.2
ADC1.3
CS0.12
A17m/ LSI0 Yes
A9
INT0.0
INT1.0
ADC1.2
CS0.13
WAKE.3
PB2.1
PB2.2
PB2.3
PB2.4
PB2.5
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
36 A21 XBR1
35 B16 XBR1
34 A20 XBR1
31 B14 XBR1
30 A18 XBR1
A16m/ LSI1 Yes
A8
INT0.1
INT1.1
WAKE.4
ADC1.1
CS0.14
AD15m/ LSI2 Yes
A7
INT0.2
INT1.2
WAKE.5
ADC1.0
CS0.15
PMU_Asleep
AD14m/ LSI3 Yes
A6
INT0.3
INT1.3
WAKE.6
AD13m/ LSI4 Yes
A5
INT0.4
INT1.4
WAKE.7
AD12m / LSI5 Yes
A4
INT0.5
INT1.5
Preliminary Rev. 0.8
53
SILICON [ SILICON ]
