SiM3C1xx
4.8. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
Clocks to all AHB peripherals are enabled.
Clocks to all APB peripherals other than Watchdog Timer, EMIF0, and DMAXBAR are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VDD Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. The Watchdog Timer is enabled with the Low Frequency Oscillator (LFO0) as its clock source. Program
execution begins at location 0x00000000.
Reset Sources
RESET
VDD Supply
Monitor
Missing Clock
Detector
Watchdog Timer
Software Reset
system reset
Comparator 0
Comparator 1
RTC0 Alarm
PMU / Wakeup
Core Reset
Preliminary Rev. 0.8
47
SILICON [ SILICON ]
