SiM3C1xx
Spike suppression up to 2 times the APB period.
2
4.6.6. I S (I2S0)
2
2
The I S module receives digital data from an external source over a data line in the standard I S, left-justified, right-
justified, or time domain multiplexing format, de-serializes the data, and generates requests to transfer the data
using the DMA. The module also reads stereo audio samples from the DMA, serializes the data, and sends it out of
2
the chip on a data line in the same standard serial format for digital audio. The I S receive interface consists of 3
signals: SCK (bit clock), WS (word select or frame sync), and SD (data input). The block’s transmit interface
consists of 3 signals: SCK (bit clock), WS (word select or frame sync) and SD (data output).
2
The I S module includes the following features:
Master or slave capability.
Flexible 10-bit clock divider with 8-bit fractional clock divider provides support for various common
sampling frequencies (16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz) for up to two 32-bit
channels.
Support for DMA data transfers.
Support for various data formats.
44
Preliminary Rev. 0.8
SILICON [ SILICON ]
