Si52147
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
PWR 3.3 V Power Supply
34
VDD
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
35
36
37
38
39
DIFF8
DIFF8
I
SMBus compatible SCLOCK
SCLK
I/O SMBus compatible SDATA
I, PU
SDATA
CKPWRGD_PDB
3.3 V CMOS input. A real-time active low input for asserting power
down (PDB) and disabling all outputs (internal 100 k pull-up).
PWR 3.3 V Power Supply
40
41
42
43
44
45
46
47
48
49
VDD_CORE
XOUT
XIN/CLKIN
NC
O
I
25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input
NC No Connect
NC No Connect
GND Ground
NC
VSS_CORE
VSS
GND Ground
NC No Connect
NC No Connect
NC
NC
GND
GND Ground for bottom pad of the IC.
Preliminary Rev. 0.1
19
SILICON [ SILICON ]
