Si52147
5. Pin Descriptions: 48-Pin QFN
48
47
46
45
44
43
42
41
40
39
38
37
DIFF8
DIFF8
36
35
34
33
VDD
1
2
3
4
5
6
7
8
9
VDD
OE01
VDD
DIFF7
OE11
32 DIFF7
SSON2
VSS_PLL3
VSS_PLL4
OE21
31
30
29
28
DIFF6
DIFF6
49
GND
VDD
OE31
DIFF5
27 DIFF5
OE[4:5]1 10
DIFF4
DIFF4
26
25
OE[6:8]1
11
12
VDD
13
14
15
16
17
18
19
20
21
22
23
24
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
PWR 3.3 V Power Supply
1
VDD
PWR 3.3 V Power Supply
2
3
VDD
OE0
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
4
5
6
OE1
SSON
VSS
Refer to Table 1 on page 4 for OE specifications.
I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks (internal
100 k pull-down)
GND Ground
Preliminary Rev. 0.1
17
SILICON [ SILICON ]
