Si52147
Table 7. Part Number 48-Pin QFN Descriptions
Pin #
Name
Type
Description
GND Ground
7
VSS
OE2
I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up).
8
9
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up).
OE3
Refer to Table 1 on page 4 for OE specifications.
I,PU
10
OE[4:5]
3.3 V input to disable DIFF[4:5] (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF[6:8] (internal 100 k pull-up).
11
OE[6:8]
Refer to Table 1 on page 4 for OE specifications.
PWR 3.3 V Power Supply
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
VDD
PWR 3.3 V Power Supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
VSS Ground
DIFF0
DIFF0
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3V Power Supply
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
VDD
GND Ground
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
GND Ground
DIFF4
DIFF4
DIFF5
DIFF5
VSS
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
DIFF6
DIFF6
DIFF7
DIFF7
18
Preliminary Rev. 0.1
SILICON [ SILICON ]
