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SI4020 参数 Datasheet PDF下载

SI4020图片预览
型号: SI4020
PDF下载: 下载PDF文件 查看货源
内容描述: 完全集成( IOW BOM ,易于设计的)无生产快速稳定所需的对齐方式,可编程,高清晰度PLL [Fully integrated (Iow BOM, easy design-in) No alignment required in production Fast settling, programmable, high-resolution PLL]
分类和应用:
文件页数/大小: 32 页 / 1064 K
品牌: SILICON [ SILICON ]
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Si4020  
AC Characteristics  
Symbol  
Parameter  
Conditions/Notes  
Min  
8
Typ  
Max  
12  
Units  
fref  
PLL reference frequency  
Crystal operation mode is parallel (Note 2)  
315 MHz band, 2.5 kHz resolution  
433 MHz band, 2.5 kHz resolution  
868 MHz band, 5.0 kHz resolution  
915 MHz band, 7.5 kHz resolution  
10  
MHz  
310.24  
430.24  
860.48  
900.72  
319.75  
439.75  
879.51  
929.27  
fo  
Output frequency (programmable)  
MHz  
µs  
Frequency error < 10 kHz after 10 MHz  
step  
tlock  
PLL lock time  
20  
After turning on from idle mode, with  
crystal oscillator already stable  
tsp  
PLL startup time  
250  
2.5  
µs  
IOUT  
Open collector output current (Note 3) At all bands  
0.1  
mA  
Available output power  
(315 and 433 MHz band)  
With optimal antenna impedance  
(Note 4)  
PmaxL  
3
1
dBm  
Available output power  
(868 and 915 MHz band)  
With optimal antenna impedance  
(Note 4)  
PmaxH  
Pout  
dBm  
dBm  
dBc  
Typical output power  
Selectable in 3 dB steps (Note3)  
Pmax-21  
Pmax  
-50  
At max power with loop antenna  
(Note 5)  
Psp  
Spurious emission  
At low bands  
At high bands  
1.5  
1.6  
2.3  
2.2  
3.1  
2.8  
Output capacitance (set by the  
automatic antenna tuning circuit)  
Co  
pF  
Quality factor of the output  
capacitance  
Qo  
16  
18  
22  
100 kHz from carrier  
1 MHz from carrier  
-75  
-85  
Lout  
Output phase noise  
dBc/Hz  
BRFSK  
BROOK  
dffsk  
FSK bit rate  
256  
512  
240  
kbps  
kbps  
kHz  
OOK bit rate  
FSK frequency deviation  
Programmable in 30 kHz steps  
30  
Crystal load capacitance  
See Crystal Selection Guidelines  
Programmable in 0.5 pF steps, tolerance  
+/- 10%  
Cxl  
8.5  
16  
pF  
Internal POR timeout  
(Note 6)  
tPOR  
tsx  
After Vdd has reached 90% of final value  
Crystal ESR < 100 Ohms (Note 7)  
100  
5
ms  
ms  
Crystal oscillator startup time  
1
Crystal oscillator must be enabled to  
ensure proper calibration at startup  
(Note 7)  
tPBt  
Wake-up timer clock accuracy  
+/-10%  
ms  
twake-up  
Cin, D  
tr, f  
Programmable wake-up time  
Digital input capacitance  
Digital output rise/fall time  
1
2 · 109  
2
ms  
pF  
ns  
15 pF pure capacitive load  
10  
All notes for table above are on page 7.  
8
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