Si3056
Si3018/19/10
Register 59. Spark Quenching Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TB3
R/W
SQ1
R/W
SQ0
R/W
RG1
R/W
GCE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
TB3
For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize a ringer
impedance to meet South Korea ringer impedance requirements. This bit should only be set
to meet South Korea PTT requirements and should only be set in conjunction with the RZ bit.
Spark Quenching.
6
SQ1
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
Mean On-Hook Speed
Less than 0.5 ms
0
0
1
0
1
X
00
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching
spec)
11
5
4
Reserved Always write this bit to zero.
Spark Quenching.
SQ0
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
Mean On-Hook Speed
Less than 0.5 ms
0
0
1
0
1
X
00
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching
spec)
11
3
2
Reserved Always write this bit to zero.
Receive Gain 1 (Line-side Revision E or later).
RG1
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
Guarded Clear Enable (Line-side Revision E or later).
1
0
GCE
This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
Reserved Always write this bit to zero.
82
Rev. 1.05
SILICON [ SILICON ]
