Si3056
Si3018/19/10
7. Pin Descriptions: Si3056
MCLK
1
16
OFHK
RGDT/FSD/M1
M0
VA
GND
AOUT/INT
C1A
C2A
FSYNC
SCLK
VD
SDO
SDI
2
3
4
5
6
15
14
13
12
11
10
9
FC/RGDT
RESET
7
8
Table 24. Si3056 Pin Descriptions
Description
Pin #
Pin Name
1
MCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal clock or
modem/DSP.
2
3
4
5
6
FSYNC
SCLK
Frame Sync Output.
Data framing signal that indicates the start and stop of a communication/data frame.
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
V
Digital Supply Voltage.
Provides the 3.3 V digital supply voltage to the Si3056.
D
SDO
SDI
Serial Port Data Out.
Serial communication data that is provided by the Si3056 to the modem/DSP.
Serial Port Data In.
Serial communication and control data that is generated by the modem/DSP and pre-
sented as an input to the Si3056.
7
FC/RGDT
Secondary Transfer Request Input/Ring Detect.
An optional signal to instruct the Si3056 that control data is being requested in a sec-
ondary frame. When daisy chain is enabled, this pin becomes the ring detect output.
Produces an active low rectified version of the ring signal.
8
9
RESET
C2A
Reset Input.
An active low input that resets all control registers to a defined, initialized state. Also
used to bring the Si3056 out of sleep mode.
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor C2. Used to communicate with the line-
side device.
10
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicate with the line-
side device.
84
Rev. 1.05
SILICON [ SILICON ]
