Si1000/1/2/3/4/5
24. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
2
Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 24.1.
SMB0CN
SMB0CF
M T S S A A A S
E
I
B E S S S S
A X T T C R C
S M A O K B K
I
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
M
B
Y H T F C C
O O T S S
L E E 1 0
D
T
00
01
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SCL
SMBUS CONTROL LOGIC
Arbitration
FILTER
Interrupt
Request
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
SCL
Control
C
R
O
S
S
B
A
R
N
Hardware Slave Address Recognition
Hardware ACK Generation
Port I/O
Data Path
SDA
Control
IRQ Generation
Control
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
S S S S S S S G S S S S S S S E
L L L L L L L C L L L L L L L H
V V V V V V V
6 5 4 3 2 1 0
V V V V V V V A
M M M M M M M C
6 5 4 3 2 1 0 K
SMB0ADR
SMB0ADM
N
Figure 24.1. SMBus Block Diagram
Rev. 1.0
287
SILICON [ SILICON ]
