Si1000/1/2/3/4/5
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power
Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in
a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automati-
cally average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional
CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
Start
Conversion
ADC0TK
Burst Mode Logic
ADC0PWR
10-bit
SAR
AIN+
From
AMUX0
16-Bit Accumulator
ADC
AD0WINT
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 1.11. ADC0 Functional Block Diagram
24
Rev. 1.0
SILICON [ SILICON ]
