Si1000/1/2/3/4/5
1.4. Serial Ports
2
The Si1000/1/2/3/4/5 family includes an SMBus/I C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is
also a dedicated EZRadioPRO Serial Interface (SPI1) to allow communication with the EZRadioPRO
peripheral.
1.5. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Addi-
tionally, Capture/Compare Module 5 offers watchdog timer capabilities. Following a system reset, Module 5
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
PCA
CLOCK
MUX
Timer0 Overflow
ECI
16 -Bit Counter/Timer
SYSCLK
External Clock 8
/
Capture/ Compare
Module0
Capture/ Compare
Module1
Capture/ Compare
Module2
Capture/ Compare
Module3
Capture/ Compare
Module4
Capture/ Compare
Module5 / WDT
Crossbar
Port I/O
Figure 1.10. PCA Block Diagram
Rev. 1.0
23
SILICON [ SILICON ]
