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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 266  
Figure 23.18. Manchester Coding Example .......................................................... 266  
Figure 23.19. Header ............................................................................................. 268  
Figure 23.20. POR Glitch Parameters ................................................................... 269  
Figure 23.21. General Purpose ADC Architecture ................................................ 272  
Figure 23.22. Temperature Ranges using ADC8 .................................................. 274  
Figure 23.23. WUT Interrupt and WUT Operation ................................................. 277  
Figure 23.24. Low Duty Cycle Mode ..................................................................... 278  
Figure 23.25. RSSI Value vs. Input Power ............................................................ 280  
Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 281  
Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 282  
Figure 24.1. SMBus Block Diagram ...................................................................... 287  
Figure 24.2. Typical SMBus Configuration ............................................................ 288  
Figure 24.3. SMBus Transaction ........................................................................... 289  
Figure 24.4. Typical SMBus SCL Generation ........................................................ 291  
Figure 24.5. Typical Master Write Sequence ........................................................ 302  
Figure 24.6. Typical Master Read Sequence ........................................................ 303  
Figure 24.7. Typical Slave Write Sequence .......................................................... 304  
Figure 24.8. Typical Slave Read Sequence .......................................................... 305  
Figure 25.1. UART0 Block Diagram ...................................................................... 310  
Figure 25.2. UART0 Baud Rate Logic ................................................................... 311  
Figure 25.3. UART Interconnect Diagram ............................................................. 312  
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 312  
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 313  
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 313  
Figure 26.1. SPI Block Diagram ............................................................................ 317  
Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 319  
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode  
Connection Diagram .......................................................................... 319  
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode  
Connection Diagram .......................................................................... 320  
Figure 26.5. Master Mode Data/Clock Timing ....................................................... 322  
Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 323  
Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 323  
Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 327  
Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 327  
Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 328  
Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 328  
Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 333  
Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 334  
Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 335  
Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 340  
Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 341  
Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 342  
Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 346  
12  
Rev. 1.0