Si1000/1/2/3/4/5
Figure 7.3. Comparator Hysteresis Plot ................................................................ 101
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 106
Figure 8.1. CIP-51 Block Diagram ......................................................................... 109
Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 118
Figure 9.2. Flash Program Memory Map ............................................................... 119
Figure 13.1. Flash Program Memory Map ............................................................. 143
Figure 14.1. Si1000/1/2/3/4/5 Power Distribution .................................................. 152
Figure 15.1. CRC0 Block Diagram ........................................................................ 158
Figure 15.2. Bit Reverse Register ......................................................................... 164
Figure 16.1. DC-DC Converter Block Diagram ...................................................... 165
Figure 16.2. DC-DC Converter Configuration Options .......................................... 168
Figure 18.1. Reset Sources ................................................................................... 175
Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 176
Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 177
Figure 19.1. Clocking Sources Block Diagram ...................................................... 182
Figure 19.2. 25 MHz External Crystal Example ..................................................... 184
Figure 20.1. SmaRTClock Block Diagram ............................................................. 190
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 199
Figure 21.1. Port I/O Functional Block Diagram .................................................... 207
Figure 21.2. Port I/O Cell Block Diagram .............................................................. 208
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 212
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 213
Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 228
Figure 22.2. SPI Timing ......................................................................................... 230
Figure 22.3. SPI Timing—READ Mode ................................................................. 230
Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 231
Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 231
Figure 22.6. Master Mode Data/Clock Timing ....................................................... 232
Figure 22.7. SPI Master Timing ............................................................................. 238
Figure 23.1. State Machine Diagram ..................................................................... 241
Figure 23.2. TX Timing .......................................................................................... 244
Figure 23.3. RX Timing .......................................................................................... 245
Figure 23.4. Frequency Deviation ......................................................................... 248
Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 250
Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 252
Figure 23.7. Direct Synchronous Mode Example .................................................. 255
Figure 23.8. Direct Asynchronous Mode Example ................................................ 255
Figure 23.9. Microcontroller Connections .............................................................. 256
Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 258
Figure 23.11. FIFO Thresholds ............................................................................. 261
Figure 23.12. Packet Structure .............................................................................. 262
Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 263
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 263
Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 264
Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 264
Rev. 1.0
11
SILICON [ SILICON ]
