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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
26.4. SPI0 Interrupt Sources  
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to  
logic 1:  
All of the following bits must be cleared by software.  
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can  
occur in all SPI0 modes.  
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when  
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to  
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0  
modes.  
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for  
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN  
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.  
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a  
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new  
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The  
data byte which caused the overrun is lost.  
Rev. 1.0  
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