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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
26. Enhanced Serial Peripheral Interface (SPI0)  
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous  
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports  
multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an  
input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment,  
avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers.  
NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation.  
Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.  
SFR Bus  
SPI0CKR  
SPI0CFG  
SPI0CN  
Clock Divide  
Logic  
SYSCLK  
SPI CONTROL LOGIC  
SPI IRQ  
Data Path  
Control  
Pin Interface  
Control  
MOSI  
Tx Data  
C
R
O
S
S
B
A
R
SPI0DAT  
SCK  
MISO  
NSS  
Transmit Data Buffer  
Pin  
Control  
Logic  
Port I/O  
Shift Register  
Rx Data  
7 6 5 4 3 2 1 0  
Receive Data Buffer  
Read  
SPI0DAT  
Write  
SPI0DAT  
SFR Bus  
Figure 26.1. SPI Block Diagram  
Rev. 1.0  
317