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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
26.5. Serial Clock Phase and Polarity  
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the  
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases  
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low  
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0  
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The  
clock and data line relationships for master mode are shown in Figure 26.5. For slave mode, the clock and  
data relationships are shown in Figure 26.6 and Figure 26.7. Note that CKPHA should be set to 0 on both  
the master and slave SPI when communicating between two Silicon Labs C8051 devices.  
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 26.9 controls the master mode  
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured  
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,  
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for  
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-  
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master  
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)  
must be less than 1/10 the system clock frequency. In the special case where the master only wants to  
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the  
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.  
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s  
system clock.  
SCK  
(CKPOL=0, CKPHA=0)  
SCK  
(CKPOL=0, CKPHA=1)  
SCK  
(CKPOL=1, CKPHA=0)  
SCK  
(CKPOL=1, CKPHA=1)  
MISO/MOSI  
MSB  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
NSS (Must Remain High  
in Multi-Master Mode)  
Figure 26.5. Master Mode Data/Clock Timing  
322  
Rev. 1.0