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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the  
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in  
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,  
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if  
enabled when either TI0 or RI0 is set to 1.  
MARK  
START  
BIT  
STOP  
BIT  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
SPACE  
BIT TIMES  
BIT SAMPLING  
Figure 25.5. 9-Bit UART Timing Diagram  
25.3. Multiprocessor Communications  
9-Bit UART mode supports multiprocessor communication between a master processor and one or more  
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or  
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte  
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.  
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is  
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address  
byte has been received. In the UART interrupt handler, software will compare the received address with  
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable  
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0  
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the  
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-  
sions until it receives the next address byte.  
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple  
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master  
processor can be configured to receive all transmissions or a protocol can be implemented such that the  
master/slave role is temporarily reversed to enable half-duplex transmission between the original master  
and slave(s).  
Master  
Device  
Slave  
Device  
Slave  
Device  
Slave  
Device  
V+  
RX  
TX  
RX  
TX  
RX  
TX  
RX  
TX  
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram  
Rev. 1.0  
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