Si1000/1/2/3/4/5
mode it will be the data to be modulated and transmitted. In RX mode it will be the received demodulated
data. Figure 23.9 demonstrates using MOSI and MISO as the TX/RX data and clock:
TX on
command
TX off
command
RX on
command
RXoff
command
TX mode
RX mode
NSS
SPI input
don’t care
don’t care
SPI input
MOD input
SPI input
don’t care
don’t care
SPI input
Data output
SPI input
MOSI
MSIO
Data CLK
Output
Data CLK
Output
SPI output
SPI output
SPI output
SPI output
SPI output
Figure 23.9. Microcontroller Connections
If the MISO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by
programming Reg 0Eh bit 3.
23.4.3. PN9 Mode
In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The
primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having
to provide data.
23.5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
23.5.1. RX LNA
Depending on the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides
gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of
gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the
gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal
performance.
In the Si1002/3, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available
on www.silabs.com. When the direct tie is used the lna_sw bit in Register 6Dh, TX Power must be set.
23.5.2. RX I-Q Mixer
The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented
as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer
consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs
are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programma-
ble gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating
between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO out-
put.
23.5.3. Programmable Gain Amplifier
The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the
dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals
to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC
algorithm in the digital modem.
256
Rev. 1.0
SILICON [ SILICON ]
