Si1000/1/2/3/4/5
VDD_DIG
Px.x
VDD_RF
TX
Direct synchronous modulation. Full
control over the serial interface & using
interrupt. Bitrate clock and modulation
via GPIO’s.
RXp
RXn
NC
Px.x
Matching
GPIO configuration
GP1 : TX DATA clock output
GP2 : TX DATA input
DataCLK
MOD(Data)
Figure 23.7. Direct Synchronous Mode Example
Direct asynchronous FSK modulation.
Modulation data via GPIO2, no data
clock needed in this mode.
VDD_DIG
Px.x
VDD_RF
TX
RXp
RXn
NC
Matching
GPIO configuration
GP2 : TX DATA input
MOD(Data)
Figure 23.8. Direct Asynchronous Mode Example
23.4.2.5. Direct Mode using SPI or nIRQ Pins
It is possible to use the EZRadioPRO Serial Interface signals and nIRQ as the modulation clock and data.
The MISO signal can be configured to be the data clock by programming trclk = 10. If the NSS signal is
LOW then the function of the MISO signal will be SPI data output. If the NSS signal is high and trclk[1:0] is
10 then during RX and TX modes the data clock will be available on the MISO signal. If trclk[1:0] is set to
11 and no interrupts are enabled in registers 05 or 06h, then the nIRQ pin can also be used as the TX/RX
data clock.
Note: The MISO and NSS signals are internal connections. The nIRQ signal is accessed through an
external package pin.
The MOSI signal can be configured to be the data source in both RX and TX modes if dtmod[1:0] = 01. In
a similar fashion, if NSS is LOW the MOSI signal will function as SPI data-in. If NSS is HIGH then in TX
Rev. 1.0
255
SILICON [ SILICON ]
