Si1000/1/2/3/4/5
22.1. Signal Descriptions
The four signals used by SPI1 (MOSI, MISO, SCK, NSS) are described below.
22.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output from the MCU core
and an input to the EZRadioPRO peripheral. Data is transferred most-significant bit first. MOSI is driven by
the MSB of the shift register.
22.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to master devices. It
is used to serially transfer data from the EZRadioPRO to the MCU core. This signal is an input to the MCU
core and an output from the EZRadioPRO peripheral. Data is transferred most-significant bit first. The
MISO pin is placed in a high-impedance state when the SPI module is disabled.
22.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI1 gen-
erates this signal.
22.1.4. Slave Select (NSS)
Since SPI1 operates in three wire mode, the NSS functionality built into the SPI state machine is not used.
Instead, a Port pin must be configured to control the chip select on the EZRadioPRO peripheral.
22.2. SPI Master Operation on the MCU Core Side
A SPI master device initiates all data transfers on a SPI bus. SPI1 is placed in master mode by setting the
Master Enable flag (MSTENn, SPI1CN.6). Writing a byte of data to the SPI1 data register (SPI1DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI1 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF1 (SPI1CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI1 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI1DAT.
22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side
The EZRadioPRO peripheral presents a standard 4-wire SPI interface: SCK, MISO, MOSI and NSS. The
SPI master can read data from the device on the MOSI output pin. A SPI transaction is a 16-bit sequence
which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data
field (DATA) as demonstrated in Figure 22.2. The 7-bit address field is used to select one of the 128, 8-bit
control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction.
If R/W = 1 it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents
(ADDR or DATA) are latched into the transceiver every eight clock cycles. The timing parameters for the
SPI interface are shown in Table 22.1. The SCK rate is flexible with a maximum rate of 10 MHz.
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SILICON [ SILICON ]
