欢迎访问ic37.com |
会员登录 免费注册
发布采购

SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
 浏览型号SI1003的Datasheet PDF文件第221页浏览型号SI1003的Datasheet PDF文件第222页浏览型号SI1003的Datasheet PDF文件第223页浏览型号SI1003的Datasheet PDF文件第224页浏览型号SI1003的Datasheet PDF文件第226页浏览型号SI1003的Datasheet PDF文件第227页浏览型号SI1003的Datasheet PDF文件第228页浏览型号SI1003的Datasheet PDF文件第229页  
Si1000/1/2/3/4/5  
SFR Definition 21.17. P1DRV: Port1 Drive Strength  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
P1DRV[7:0]  
R/W  
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA5  
Bit Name  
7:0 P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectively).  
Function  
Configures digital I/O Port cells to high or low output drive strength.  
0: Corresponding P1.n Output has low output drive strength.  
1: Corresponding P1.n Output has high output drive strength.  
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not externally or  
internally connected.  
SFR Definition 21.18. P2: Port2  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
P2[7:0]  
R/W  
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable  
Bit  
Name  
P2[7:0] Port 2 Data.  
Sets the Port latch logic  
Description  
Read  
0: Set output latch to logic 0: P2.n Port pin is logic  
LOW. LOW.  
1: Set output latch to logic 1: P2.n Port pin is logic  
Write  
7:0  
value or reads the Port pin  
logic state in Port cells con-  
figured for digital I/O.  
HIGH.  
HIGH.  
Rev. 1.0  
225  
 复制成功!