Si1000/1/2/3/4/5
22. EZRadioPRO® Serial Interface (SPI1)
The EZRadioPRO serial interface (SPI1) provides access to the EZRadioPRO peripheral registers from
software executing on the MCU core. The serial interface consists of two SPI peripherals -- a dedicated
SPI Master accessible from the MCU core and dedicated SPI Slave residing inside the EZRadioPRO
peripheral. The SPI1 peripheral on the MCU core side can only be used in master mode to communicate
with the EZRadioPRO slave device in three wire mode. NSS for the EZRadioPRO is provided using Port
1.4, which is internally routed to the EZRadioPRO peripheral. The EZRadioPRO Serial Interface provides
a system interrupt to regulate SPI traffic between the MCU core and the EZRadioPRO peripheral. This
interrupt is internally routed to the MCU core. The EZRadioPRO peripheral also has an nIRQ pin which
should be routed external to the package back into an external interrupt pin. The nIRQ interrupt pin is
independent of the EZRadioPRO Serial Interface.
SFR Bus
SPI1CKR
SPI1CFG
SPI1CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
EZRadioPRO Serial Interface (SPI1) IRQ
Data Path
Control
Pin Interface
Control
P1.0
SCK
SCK
Tx Data
C
R
O
S
S
B
A
R
SPI1DAT
P1.1
MISO
MOSI
NSS
MISO
Transmit Data Buffer
Pin
Control
Logic
EZRadioPRO
Peripheral
Shift Register
P1.2
P1.4
MOSI
NSS
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 22.1. EZRadioPRO Serial Interface Block Diagram
228
Rev. 1.0
SILICON [ SILICON ]
