EFR32MG13P732F512IM32-D 参数 Datasheet PDF下载

型号：	EFR32MG13P732F512IM32-D
PDF下载：	下载PDF文件查看货源
内容描述：	[EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet]
分类和应用：	无线
文件页数/大小：	194 页 / 2303 K
品牌：	SILICON [ SILICON ]

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EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Start up time

t_{IDAC_SU}

Output within 1% of steady state

value

—

µs

Settling time, (output settled t_{IDAC_SETTLE}

within 1% of steady state val-

ue),

Range setting is changed

Step value is changed

—

µs

Current consumption²

I_IDAC

EM0 or EM1 Source mode, ex-

cluding output current, Across op-

erating temperature range

—

µA

EM0 or EM1 Sink mode, exclud-

ing output current, Across operat-

ing temperature range

—

µA

EM2 or EM3 Source mode, ex-

cluding output current, T = 25 °C

—

0.023

0.041

—

µA

EM2 or EM3 Sink mode, exclud-

ing output current, T = 25 °C

EM2 or EM3 Source mode, ex-

cluding output current, T ≥ 85 °C

EM2 or EM3 Sink mode, exclud-

ing output current, T ≥ 85 °C

RANGESEL¹= RANGE0, output

Output voltage compliance in I_{COMP_SRC}

source mode, source current

change relative to current

sourced at 0 V

0.11

voltage = min(V_IOVDD

V_AVDD²-100 mV)

RANGESEL¹= RANGE1, output

—

0.06

0.04

0.03

—

voltage = min(V_IOVDD

V_AVDD²-100 mV)

RANGESEL¹= RANGE2, output

voltage = min(V_IOVDD

V_AVDD²-150 mV)

RANGESEL¹= RANGE3, output

voltage = min(V_IOVDD

V_AVDD²-250 mV)

RANGESEL¹= RANGE0, output

voltage = 100 mV

Output voltage compliance in I_{COMP_SINK}

sink mode, sink current

change relative to current

sunk at IOVDD

—

0.12

0.05

0.04

0.03

—

RANGESEL¹= RANGE1, output

voltage = 100 mV

RANGESEL¹= RANGE2, output

voltage = 150 mV

RANGESEL¹= RANGE3, output

voltage = 250 mV

Note:

1. In IDAC_CURPROG register.

2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and

PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-

tween AVDD (0) and DVDD (1).

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EFR32MG13P732F512IM32-D 参数 Datasheet PDF下载

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