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EFR32MG13P732F512IM32-D 参数 Datasheet PDF下载

EFR32MG13P732F512IM32-D图片预览
型号: EFR32MG13P732F512IM32-D
PDF下载: 下载PDF文件 查看货源
内容描述: [EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet]
分类和应用: 无线
文件页数/大小: 194 页 / 2303 K
品牌: SILICON [ SILICON ]
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EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet  
System Overview  
3.2.5 Wake on Radio  
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-  
ing a subsystem of the EFR32MG13 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-  
als.  
3.2.6 RFSENSE  
The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid-  
ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.  
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-  
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by  
enabling normal RF reception.  
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using  
available timer peripherals.  
3.2.7 Flexible Frame Handling  
EFR32MG13 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.  
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-  
tor:  
• Highly adjustable preamble length  
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts  
• Frame disassembly and address matching (filtering) to accept or reject frames  
• Automatic ACK frame assembly and transmission  
• Fully flexible CRC generation and verification:  
• Multiple CRC values can be embedded in a single frame  
• 8, 16, 24 or 32-bit CRC value  
• Configurable CRC bit and byte ordering  
• Selectable bit-ordering (least significant or most significant bit first)  
• Optional data whitening  
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding  
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing  
• Optional symbol interleaving, typically used in combination with FEC  
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware  
• UART encoding over air, with start and stop bit insertion / removal  
• Test mode support, such as modulated or unmodulated carrier output  
• Received frame timestamping  
3.2.8 Packet and State Trace  
The EFR32MG13 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  
It features:  
• Non-intrusive trace of transmit data, receive data and state information  
• Data observability on a single-pin UART data output, or on a two-pin SPI data output  
• Configurable data output bitrate / baudrate  
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream  
3.2.9 Data Buffering  
The EFR32MG13 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  
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