C8051F52x-53x
9. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The C8051F52x/C8051F53x family has a superset of all the peripherals included with a standard
8051. See Section “1. System Overview” on page 17 for more information about the available peripherals.
The CIP-51 includes on-chip debug hardware which interfaces directly with the analog and digital sub-
systems, providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 core includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput
- 256 Bytes of Internal RAM
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- Integrated Debug Logic
- Program and Data Memory Security
DATA BUS
ACCUMULATOR
B REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
PSW
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
DATA POINTER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 9.1. CIP-51 Block Diagram
Rev. 0.3
75
SILICON [ SILICON ]
