C8051F52x-53x
17.3.2. LIN Indirect Access SFR Registers Definition
Table 17.1. LIN Registers* (Indirectly Addressable)
Addres
s
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LINDT1
LINDT2
LINDT3
LINDT4
LINDT5
LINDT6
LINDT7
LINDT8
LINCTRL
LINST
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
data byte 0[7:0]
data byte 1[7:0]
data byte 2[7:0]
data byte 3[7:0]
data byte 4[7:0]
data byte 5[7:0]
data byte 6[7:0]
data byte 7[7:0]
STOP(s) SLEEP(s)
TXRX
DTACK(s) RSTINT RSTERR WUPREQ STREQ(m)
ACTIVE
IDLTOUT ABORT(s) DTREQ(s) LININT ERROR WAKEUP
SYNCH(s) PRTY(s) TOUT CHK
data length [3:0]
DONE
LINERR
LINSIZE
LINDIV
LINMUL
LINID
BITERR
ENHCHK
baud divider[7:0]
PRESCL1 PRESCL0
MUL4
ID5
MUL3
ID4
MUL2
ID3
MUL1
ID2
MUL0
ID1
DIV
ID0
*These registers are used in both master and slave mode. The register bits marked with (m) are
accessible only in Master mode while the register bits marked with (s) are accessible only in slave
mode. All other registers are accessible in both modes.
SFR Definition 17.4. LINDT1: LIN Data Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Reset Value
00000000
Bit0
0x00
(indirect)
SFR Address:
Bit7–0: LINDT1: Serial Data Byte Received or transmitted by the interface
154
Rev. 0.3
SILICON [ SILICON ]
