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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
5.2. Electrical Characteristics  
Table 5.2. Global Electrical Characteristics  
–40 to +125 °C, 24 MHz system clock unless otherwise specified.  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Supply Input Voltage (V  
)
1.8  
5.25  
V
REGIN  
1
1
Digital Supply Voltage (V  
)
System Clock < 25 MHz  
System Clock > 25 MHz  
2.75  
2.75  
2.75  
2.75  
DD  
V
RST  
V
V
2
Analog Supply Voltage (VDDA) System Clock < 25 MHz  
V
RST  
2
(Must be connected to V  
)
System Clock > 25 MHz  
Normal Operation  
DD  
Digital Supply RAM Data  
Retention Voltage  
1.5  
2
Port I/O Supply Voltage (V )  
5.25  
50  
V
MHz  
ns  
IO  
1.8  
0
3
SYSCLK (System Clock)  
T
T
(SYSCLK High Time)  
(SYSCLK Low Time)  
9
9
SYSH  
SYSL  
ns  
Specified Operating  
Temperature Range  
–40  
+125  
°C  
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)  
4
V
V
V
V
= 2.1 V, F = 200 kHz  
= 2.1 V, F = 1.5 MHz  
= 2.1 V, F = 25 MHz  
= 2.1 V, F = 50 MHz  
95  
700  
10  
11  
21  
µA  
µA  
I
DD  
DD  
DD  
DD  
DD  
mA  
mA  
19  
Notes:  
1. Given in Table 5.4 on page 46.  
2. VIO should not be lower than the VDD voltage.  
3. SYSCLK must be at least 32 kHz to enable debugging.  
4. Based on device characterization data; Not production tested. Does not include oscillator supply current.  
5. IDD can be estimated for frequencies < 12.5 MHz by simply multiplying the frequency of interest by the  
frequency sensitivity number for that range. When using these numbers to estimate IDD for >12.5 MHz, the  
estimate should be the current at 50 MHz minus the difference in current indicated by the frequency  
sensitivity number. For example: VDD = 2.6 V; F = 20 MHz, IDD = 26 mA - (50 MHz -  
20 MHz) * 0.48 mA/MHz = 11.6 mA.  
6. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the  
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the  
estimate should be the current at 50 MHz minus the difference in current indicated by the frequency  
sensitivity number.   
For example: VDD = 2.6 V; F = 5 MHz, Idle IDD = 21 mA – (50 MHz – 5 MHz) x 0.41 mA/MHz = 2.6 mA.  
Rev. 1.1  
41  
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