C8051F50x-F51x
SFR Definition 23.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
MASTER TXMODE
STA
STO
ACKRQ ARBLOST
ACK
SI
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
SFR Address = 0xC0; Bit-Addressable; SFR Page =0x00
Bit
Name
Description
Read
Write
7
MASTER SMBus Master/Slave
Indicator. This read-only bit
0: SMBus operating in
slave mode.
N/A
N/A
indicates when the SMBus is 1: SMBus operating in
operating as a master.
master mode.
6
5
4
TXMODE SMBus Transmit Mode
Indicator. This read-only bit
0: SMBus in Receiver
Mode.
indicates when the SMBus is 1: SMBus in Transmitter
operating as a transmitter.
Mode.
STA
STO
SMBus Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
SMBus Stop Flag.
0: No Stop condition
detected.
0: No STOP condition is
transmitted.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode).
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
2
1
0
ACKRQ SMBus Acknowledge
0: No Ack requested
1: ACK requested
N/A
N/A
Request.
ARBLOST SMBus Arbitration Lost
0: No arbitration error.
1: Arbitration Lost
Indicator.
ACK
SI
SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
234
Rev. 1.1
SILICON [ SILICON ]
