欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F502-IM的Datasheet PDF文件第199页浏览型号C8051F502-IM的Datasheet PDF文件第200页浏览型号C8051F502-IM的Datasheet PDF文件第201页浏览型号C8051F502-IM的Datasheet PDF文件第202页浏览型号C8051F502-IM的Datasheet PDF文件第204页浏览型号C8051F502-IM的Datasheet PDF文件第205页浏览型号C8051F502-IM的Datasheet PDF文件第206页浏览型号C8051F502-IM的Datasheet PDF文件第207页  
C8051F50x-F51x  
Use the following equations to calculate the values for the variables for the baud-rate equation:  
20000  
multiplier = ----------------------------- 1  
baud_rate  
SYSCLK  
1
ln2  
------------------------------------------------------------------------------------------------  
prescaler = ln  
-------- 1  
multiplier + 1baud_rate 200  
SYSCLK  
divider = -------------------------------------------------------------------------------------------------------------------------------------  
prescaler + 1  
2  
multiplier + 1baud_rate  
In all of these equations, the results must be rounded down to the nearest integer.  
The following example shows the steps for calculating the baud rate values for a Master node running at  
24 MHz and communicating at 19200 bits/sec. First, calculate the multiplier:  
20000  
multiplier = ---------------- 1 = 0. 0417 0  
19200  
Next, calculate the prescaler:  
24000000  
1
ln2  
-----------------------------------------------------------  
prescaler = ln  
-------- 1 = 1.644 1  
0 + 119200 200  
Finally, calculate the divider:  
24000000  
divider = ---------------------------------------------------------------------- = 312.5 312  
1 + 1  
2
0 + 119200  
These values lead to the following baud rate:  
24000000  
----------------------------------------------------------------  
2
baud_rate =  
19230.77  
1 + 1  
0 + 1312  
The following code programs the interface in Master mode, using the Enhanced Checksum and enables  
the interface to operate at 19230 bits/sec using a 24 MHz system clock.  
LIN0CF  
LIN0CF |= 0x40;  
= 0x80;  
// Activate the interface  
// Set the node as a Master  
LIN0ADR = 0x0D;  
// Point to the LIN0MUL register  
// Initialize the register (prescaler, multiplier and bit 8 of divider)  
LIN0DAT = ( 0x01 << 6 ) + ( 0x00 << 1 ) + ( ( 0x138 & 0x0100 ) >> 8 );  
LIN0ADR  
LIN0DAT  
= 0x0C;  
= (unsigned char)_0x138;  
// Point to the LIN0DIV register  
// Initialize LIN0DIV  
LIN0ADR  
= 0x0B;  
// Point to the LIN0SIZE register  
LIN0DAT |= 0x80;  
// Initialize the checksum as Enhanced  
LIN0ADR  
LIN0DAT  
= 0x08;  
= 0x0C;  
// Point to LIN0CTRL register  
// Reset any error and the interrupt  
Rev. 1.1  
203