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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F502-IM的Datasheet PDF文件第191页浏览型号C8051F502-IM的Datasheet PDF文件第192页浏览型号C8051F502-IM的Datasheet PDF文件第193页浏览型号C8051F502-IM的Datasheet PDF文件第194页浏览型号C8051F502-IM的Datasheet PDF文件第196页浏览型号C8051F502-IM的Datasheet PDF文件第197页浏览型号C8051F502-IM的Datasheet PDF文件第198页浏览型号C8051F502-IM的Datasheet PDF文件第199页  
C8051F50x-F51x  
SFR Definition 20.19. P1SKIP: Port 1 Skip  
Bit  
7
6
5
4
3
2
1
0
P1SKIP[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xD5; SFR Page = 0x0F  
Bit  
Name  
Function  
7:0  
P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.  
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins  
used for analog, special functions or GPIO should be skipped by the Crossbar.  
0: Corresponding P1.n pin is not skipped by the Crossbar.  
1: Corresponding P1.n pin is skipped by the Crossbar.  
SFR Definition 20.20. P2: Port 2  
Bit  
7
6
5
4
3
2
1
0
P2[7:0]  
R/W  
Name  
Type  
Reset  
1
1
1
1
1
1
1
1
SFR Address = 0xA0; SFR Page = All Pages; Bit-Addressable  
Bit  
Name  
P2[7:0] Port 2Data.  
Sets the Port latch logic  
Description  
Write  
0: Set output latch to logic 0: P2.n Port pin is logic  
LOW. LOW.  
1: Set output latch to logic 1: P2.n Port pin is logic  
Read  
7:0  
value or reads the Port pin  
logic state in Port cells con-  
figured for digital I/O.  
HIGH.  
HIGH.  
Rev. 1.1  
195