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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
20.6. Special Function Registers for Accessing and Configuring Port I/O  
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte  
addressable and bit addressable, except for P4 which is only byte addressable. When writing to a Port, the  
value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic  
levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is  
assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O  
pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch reg-  
ister as the destination. The read-modify-write instructions when operating on a Port SFR are the following:  
ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individ-  
ual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified,  
and written back to the SFR.  
Ports 0–3 have a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-  
ital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital  
functions such as the EMIF should have their PnSKIP bit set to 1.  
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port  
cell can be configured for analog or digital I/O. This selection is required even for the digital resources  
selected in the XBRn registers, and is not automatic. The only exception to this is P4, which can only be  
used for digital I/O.  
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-  
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is  
required even for the digital resources selected in the XBRn registers, and is not automatic. The only  
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the  
PnMDOUT settings.  
SFR Definition 20.12. P0: Port 0  
Bit  
7
6
5
4
3
2
1
0
P0[7:0]  
R/W  
Name  
Type  
Reset  
1
1
1
1
1
1
1
1
SFR Address = 0x80; SFR Page = All Pages; Bit-Addressable  
Bit  
Name  
P0[7:0] Port 0 Data.  
Sets the Port latch logic  
Description  
Write  
0: Set output latch to logic 0: P0.n Port pin is logic  
LOW. LOW.  
1: Set output latch to logic 1: P0.n Port pin is logic  
Read  
7:0  
value or reads the Port pin  
logic state in Port cells con-  
figured for digital I/O.  
HIGH.  
HIGH.  
Rev. 1.1  
191