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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
SFR Definition 20.13. P0MDIN: Port 0 Input Mode  
Bit  
7
6
5
4
3
2
1
0
P0MDIN[7:0]  
R/W  
Name  
Type  
Reset  
1
1
1
1
1
1
1
1
SFR Address = 0xF1; SFR Page = 0x0F  
Bit  
Name  
Function  
7:0  
P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).  
Port pins configured for analog mode have their weak pull-up and digital receiver  
disabled. For analog mode, the pin also needs to be configured for open-drain  
mode in the P0MDOUT register.  
0: Corresponding P0.n pin is configured for analog mode.  
1: Corresponding P0.n pin is not configured for analog mode.  
SFR Definition 20.14. P0MDOUT: Port 0 Output Mode  
Bit  
7
6
5
4
3
2
1
0
P0MDOUT[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xA4; SFR Page = 0x0F  
Bit Name  
Function  
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).  
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.  
0: Corresponding P0.n Output is open-drain.  
1: Corresponding P0.n Output is push-pull.  
192  
Rev. 1.1