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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
SFR Definition 14.4. EIP1: Extended Interrupt Priority 1  
Bit  
7
6
5
4
3
2
1
0
PLIN0  
PT3  
PCP1  
PCP0  
PPCA0  
PADC0  
PWADC0  
PSMB0  
Name  
Type  
Reset  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
SFR Address = 0xF6; SFR Page = 0x00 and 0x0F  
Bit  
Name  
Function  
7
PLIN0  
LIN0 Interrupt Priority Control.  
This bit sets the priority of the LIN0 interrupt.  
0: LIN0 interrupts set to low priority level.  
1: LIN0 interrupts set to high priority level.  
6
5
4
3
2
1
0
PT3  
Timer 3 Interrupt Priority Control.  
This bit sets the priority of the Timer 3 interrupt.  
0: Timer 3 interrupts set to low priority level.  
1: Timer 3 interrupts set to high priority level.  
PCP1  
PCP0  
Comparator0 (CP1) Interrupt Priority Control.  
This bit sets the priority of the CP1 interrupt.  
0: CP1 interrupt set to low priority level.  
1: CP1 interrupt set to high priority level.  
Comparator0 (CP0) Interrupt Priority Control.  
This bit sets the priority of the CP0 interrupt.  
0: CP0 interrupt set to low priority level.  
1: CP0 interrupt set to high priority level.  
PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.  
This bit sets the priority of the PCA0 interrupt.  
0: PCA0 interrupt set to low priority level.  
1: PCA0 interrupt set to high priority level.  
PADC0 ADC0 Conversion Complete Interrupt Priority Control.  
This bit sets the priority of the ADC0 Conversion Complete interrupt.  
0: ADC0 Conversion Complete interrupt set to low priority level.  
1: ADC0 Conversion Complete interrupt set to high priority level.  
PWADC0 ADC0 Window Comparator Interrupt Priority Control.  
This bit sets the priority of the ADC0 Window interrupt.  
0: ADC0 Window interrupt set to low priority level.  
1: ADC0 Window interrupt set to high priority level.  
PSMB0 SMBus (SMB0) Interrupt Priority Control.  
This bit sets the priority of the SMB0 interrupt.  
0: SMB0 interrupt set to low priority level.  
1: SMB0 interrupt set to high priority level.  
124  
Rev. 1.1  
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