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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
11. Comparator0  
C8051F336/7/8/9 devices include an on-chip programmable voltage comparator, Comparator0, shown in  
Figure 11.1.  
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two  
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-  
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is  
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.  
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see  
Section “20.4. Port I/O Initialization” on page 133). Comparator0 may also be used as a reset source (see  
Section “18.5. Comparator0 Reset” on page 114).  
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section  
“11.1. Comparator Multiplexer” on page 70.  
CPT0CN  
VDD  
CP0 +  
+
CP0  
Comparator  
Input Mux  
SET  
CLR  
SET  
CLR  
D
Q
Q
D
Q
Q
CP0 -  
-
Crossbar  
(SYNCHRONIZER)  
CP0A  
GND  
Reset  
Decision  
Tree  
CPT0MD  
0
1
CP0  
Interrupt  
CP0EN  
EA  
CP0RIF  
CP0FIF  
0
0
1
1
0
1
Figure 11.1. Comparator0 Functional Block Diagram  
Rev. 0.2  
65