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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
9.1.2. Update Output Based on Timer Overflow  
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen-  
dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event.  
This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling  
rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the  
IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both  
IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0,  
Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to  
the IDAC input latches, allowing the IDAC output to change to the new value.  
9.1.3. Update Output Based on CNVSTR Edge  
The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the  
external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to  
both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The  
particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or  
both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the  
IDAC input latches, allowing the IDAC output to change to the new value.  
9.2. IDAC Output Mapping  
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC  
output word are mapped to bits 70 of the IDA0H register, and the two LSBs of the IDAC output word are  
mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 9.2.  
IDA0H  
IDA0L  
IDA09 IDA08 IDA07 IDA06 IDA05 IDA04 IDA03 IDA02 IDA01 IDA00  
Input Data Word  
(IDA09–IDA00)  
0x000  
Output Current  
IDA0OMD[1:0] = ‘1x’  
0 mA  
Output Current  
IDA0OMD[1:0] = ‘01’  
0 mA  
Output Current  
IDA0OMD[1:0] = ‘00’  
0 mA  
0x001  
0x200  
0x3FF  
1/1024 x 2 mA  
512/1024 x 2 mA  
1023/1024 x 2 mA  
1/1024 x 1 mA  
512/1024 x 1 mA  
1023/1024 x 1 mA  
1/1024 x 0.5 mA  
512/1024 x 0.5 mA  
1023/1024 x 0.5 mA  
Figure 9.2. IDA0 Data Word Mapping  
The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default,  
the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide  
full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 9.1.  
60  
Rev. 0.2