C8051F336/7/8/9
SFR Definition 7.1. ADC0CF: ADC0 Configuration
Bit
7
6
5
AD0SC[4:0]
R/W
4
3
2
AD0LJST
R/W
1
0
Name
Type
Reset
R
0
R
0
1
1
1
1
1
0
SFR Address = 0xBC
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
SYSCLK
CLKSAR
----------------------
AD0SC =
– 1
2
AD0LJST ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
1:0
UNUSED Unused. Read = 00b; Write = don’t care.
48
Rev. 0.2
SILICON [ SILICON ]
