C8051F336/7/8/9
7.1. Output Code Formatting
The ADC is in Single-ended mode when the negative input is connected to GND. The ADC will be in Differ-
ential mode when the negative input is connected to any other option. The output code format differs
between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low
bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-
justified or left-justified, depending on the setting of the AD0LJST. When in Single-ended Mode, conversion
codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF x 1023/1024.
Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H
and ADC0L registers are set to ‘0’.
Input Voltage
Right-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 1)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus-
tified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Input Voltage
Right-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 1)
VREF x 511/512
VREF x 256/512
0
0x01FF
0x0100
0x0000
0x7FC0
0x4000
0x0000
–VREF x 256/512
–VREF
0xFF00
0xFE00
0xC000
0x8000
7.2. Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
7.2.1. Starting a Conversion
A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of
Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
6. A Timer 3 overflow
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
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Rev. 0.2
SILICON [ SILICON ]
