C8051F336/7/8/9
SFR Definition 7.4. ADC0CN: ADC0 Control
Bit
7
6
AD0TM
R/W
0
5
4
3
2
1
0
Name AD0EN
AD0INT AD0BUSY AD0WINT
AD0CM[2:0]
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
0
SFR Address = 0xE8; Bit-Addressable
Bit
Name
Function
7
AD0EN
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6
AD0TM
ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Low-power Track Mode: For AD0CM[2:0] = 100, ADC is tracking when CNVSTR is
low, and conversion begins immediately on rising edge of CNVSTR.
For all other values of AD0CM[2:0], tracking is initiated on start-of-conversion event,
and lasts 3 SAR Clock cycles. The conversion immediately follows this tracking
phase.
5
4
AD0INT
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
AD0BUSY ADC0 Busy Bit.
Read:
0: ADC0 conversion is not 0: No Effect.
in progress.
1: ADC0 conversion is in sion if AD0CM[2:0] =
progress. 000b
AD0WINT ADC0 Window Compare Interrupt Flag.
Write:
1: Initiates ADC0 Conver-
3
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of ‘1’ to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
11x: Reserved.
50
Rev. 0.2
SILICON [ SILICON ]
