欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F339的Datasheet PDF文件第218页浏览型号C8051F339的Datasheet PDF文件第219页浏览型号C8051F339的Datasheet PDF文件第220页浏览型号C8051F339的Datasheet PDF文件第221页浏览型号C8051F339的Datasheet PDF文件第223页浏览型号C8051F339的Datasheet PDF文件第224页浏览型号C8051F339的Datasheet PDF文件第225页浏览型号C8051F339的Datasheet PDF文件第226页  
C8051F336/7/8/9  
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This  
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the  
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The  
total offset is then given (in PCA clocks) by Equation 25.5, where PCA0L is the value of the PCA0L register  
at the time of the update.  
Offset = (256 × PCA0CPL2) + (256 – PCA0L)  
Equation 25.5. Watchdog Timer Offset in PCA Clocks  
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and  
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF2 flag (PCA0CN.2) while the WDT is  
enabled.  
25.4.2. Watchdog Timer Usage  
To configure the WDT, perform the following tasks:  
Disable the WDT by writing a ‘0’ to the WDTE bit.  
Select the desired PCA clock source (with the CPS2CPS0 bits).  
Load PCA0CPL2 with the desired WDT update offset value.  
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle  
mode).  
Enable the WDT by setting the WDTE bit to ‘1’.  
Reset the WDT timer by writing to PCA0CPH2.  
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog  
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the  
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing  
the WDTE bit.  
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by  
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 25.5, this results in a WDT  
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 25.3 lists some example tim-  
eout intervals for typical system clocks.  
1
Table 25.3. Watchdog Timer Timeout Intervals  
System Clock (Hz)  
24,500,000  
PCA0CPL2  
Timeout Interval (ms)  
255  
128  
32  
32.1  
16.2  
4.1  
24,500,000  
24,500,000  
2
255  
257  
3,062,500  
2
128  
129.5  
3,062,500  
2
32  
255  
128  
32  
33.1  
24576  
12384  
3168  
3,062,500  
32,000  
32,000  
32,000  
Notes:  
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value  
of 0x00 at the update time.  
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.  
222  
Rev. 0.2