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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
25.4. Watchdog Timer Mode  
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used  
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified  
limit. The WDT can be configured and enabled/disabled as needed by software.  
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Mod-  
ule 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be  
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some  
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset  
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-  
ally re-configured and re-enabled if it is used in the system).  
25.4.1. Watchdog Timer Operation  
While the WDT is enabled:  
PCA counter is forced on.  
Writes to PCA0L and PCA0H are not allowed.  
PCA clock source bits (CPS2CPS0) are frozen.  
PCA Idle control bit (CIDL) is frozen.  
Module 2 is forced into software timer mode.  
Writes to the Module 2 mode register (PCA0CPM2) are disabled.  
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run  
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but  
user software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while  
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a  
write of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is  
loaded into PCA0CPH2 (See Figure 25.10).  
PCA0MD  
C W W C C C E  
I D D P P P C  
PCA0CPH2  
D T L S S S F  
L E C 2 1 0  
K
8-bit  
Comparator  
Match  
Reset  
Enable  
PCA0L Overflow  
PCA0CPL2  
8-bit Adder  
PCA0H  
Adder  
Enable  
Write to  
PCA0CPH2  
Figure 25.10. PCA Module 2 with Watchdog Timer Enabled  
Rev. 0.2  
221