C8051F336/7/8/9
14. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F336/7/8/9's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F336/7/8/9. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 14.1 lists the SFRs implemented in the C8051F336/7/8/9 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 14.2, for a detailed description of each register.
Table 14.1. Special Function Register (SFR) Memory Map
F8 SPI0CN
F0
PCA0L
PCA0H PCA0CPL0 PCA0CPH0 P0MAT
P1MDIN P2MDIN
P0MASK
EIP1
VDM0CN
PCA0PWM
RSTSRC
B
P0MDIN
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT
E0 ACC XBR0 XBR1 OSCLCN IT01CF
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
P1MASK
EIE1
SMB0ADM
D0
PSW
REF0CN
P0SKIP
TMR2L
P1SKIP
TMR2H
P2SKIP
SMB0ADR
FLKEY
C8 TMR2CN
TMR2RLL TMR2RLH
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8
B0
A8
A0
IP
IDA0CN
OSCXCN OSCICN
CLKSEL EMI0CN
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
AMX0N
AMX0P
ADC0CF
ADC0L
ADC0H
OSCICL
FLSCL
IE
P2
98 SCON0
SBUF0
CPT0CN
CPT0MD
TMR3H
TH1
CPT0MX
IDA0H
PSCTL
PCON
7(F)
90
88
80
P1
TCON
P0
TMR3CN TMR3RLL TMR3RLH
TMR3L
TH0
IDA0L
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
CKCON
0(8)
1(9)
4(C)
5(D)
6(E)
(bit addressable)
Rev. 0.2
85
SILICON [ SILICON ]
