C8051F336/7/8/9
P0
P1
P2
2 2
SF Signals
PIN I/O
VREF IDA x1
0 1 2
x2
3
CNVSTR
6
1 2
4
5
7
0
1
2
3
4
5
6
7
0
TX0
RX0
SCK
MISO
MOSI
NSS1
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:3
Port pin potentially available to peripheral
Notes:
SF Signals
1. NSS is only pinned out in 4-wire SPI Mode
2. Pins P2.1-P2.4 only on QFN24 Package
Special Function Signals are not assigned by the crossbar.
W hen these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
132
Rev. 0.2
SILICON [ SILICON ]
