C8051F336/7/8/9
20.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = ‘1’). For digital I/O pins, one of two out-
put modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = ‘1’) drive the Port pad to the VDD/DC+ or GND supply rails based on the
output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they
only drive the Port pad to GND when the output logic value is ‘0’ and become high impedance inputs (both
high low drivers turned off) when the output logic value is ‘1’.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to ‘1’. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
VDD
VDD
XBARE
(Crossbar
Enable)
(WEAK)
PORT
PAD
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
(0 for analog)
GND
To/From Analog
Peripheral
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 20.2. Port I/O Cell Block Diagram
20.1.3. Interfacing Port I/O to 5V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than VDD and less than 5.25V. An external pull-up resistor to the higher supply
voltage is typically required for most systems.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150uA to flow into the Port pin when the supply voltage is between (VDD + 0.6V) and (VDD +
1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is
minimal.
128
Rev. 0.2
SILICON [ SILICON ]
