C8051F39x/37x
9.4. ADC0 Analog Multiplexer (C8051F390/2/4/6/8 and C8051F370/4 Only)
ADC0 on the C8051F390/2/4/6/8 and C8051F370/4 has two analog multiplexers, referred to collectively as
AMUX0.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, or the positive power supply (V ). Any of the
DD
following may be selected as the negative input: Port I/O pins, V , or GND. When GND is selected as
REF
the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differ-
ential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
SFR Definition 9.9 and SFR Definition 9.10.
P0.0
AMX0P
AMUX
P2.3*
Temp
Sensor
AIN+
AIN-
VDD
P0.0
ADC0
AMUX
AMX0N
P2.3*
VREF
GND
*P2.0-P2.3 Only available as
inputs on QFN24 Packaging
Figure 9.6. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register PnSKIP. See Section “27. Port Input/Output” on page 171 for more Port I/
O configuration details.
Preliminary Rev. 0.71
59
SILICON [ SILICON ]
