C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
all pages
SFR Page:
SFR Address: 0xBA
R
R
R
–
R/W
R/W
R/W
R/W
R/W
Reset Value
–
–
AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–5: UNUSED. Read = 000b; Write = don’t care.
Bits 4–0: AMX0N4–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
AMX0N4-0
ADC0 Negative Input
(1)
(1)
00000
P1.0
(1)
(1)
00001
P1.1
(1)
(1)
00010
P1.2
(1)
(1)
00011
P1.3
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
(2)
(2)
10001
P3.1
(2)
(2)
10010
P3.2
(2)
(2)
10011
P3.3
(2)
(2)
10100
P3.4
10101–11101
11110
RESERVED
VREF
11111
GND
Notes:
1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection
RESERVED on C8051F360 (48-pin) device.
2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED
on C8051F362/7/9 (28-pin) devices.
Rev. 1.0
55
SILICON [ SILICON ]
